Phase-locked loop (PLL) circuits are able to synthesize radio frequency (RF) signals that are “locked” to a frequency reference such as a crystal oscillator or other reference. In designing a PLL, it is desirable to minimize the sensitivity of the synthesized frequency to noise coupling from other components. One way to reduce the sensitivity of the synthesized frequency is to reduce the voltage controlled oscillator (VCO) gain. Unfortunately, reducing the VCO gain also causes the frequency range of the VCO to be reduced.